1. Field of the Invention
The invention relates generally to integrated circuits, and more particularly to systems and methods of clock generation in very large scale integrated circuitry, such as a microprocessor.
2. Description of Related Art
The need and application for clock generation is ubiquitous. An exemplary, but not exclusive application can be found in a computing system wherein a processor utilizes a so-called system clock to communicate with external system devices such as DRAM, and synthesizes one or more internal clocks from the system clock to clock so-called functional units within the processor. It should be understood that a computing system is but one of many applications known to one skilled in the art for application of the present invention.
By way of background, clock generation can be broadly categorized into either phase-locked loop (PLL) circuitry or delay line loop (DLL) circuitry. PLL circuitry generally takes a reference signal, such as the system clock, compares it to a feedback signal, and generates an error signal in response thereto. The error signal drives a voltage controlled oscillator (VCO) which produces an output clock signal. The output clock signal is also scaled (typically with a divider) to generate the feedback signal for comparison with the reference signal. The divisor setting of the divider sets the frequency ratio between the reference and output clock signals. For example, if the divisor is set to three, the output clock signal will have a frequency 3.times.the frequency of the reference signal.
An advantage of PLL circuitry is elimination or substantial reduction of temporal skew between the reference signal and the output signal with proper phase comparator design. Eliminating skew is critical in applications such as, but not limited to, I/O interface timing specifications of a modern microprocessor.
A disadvantage of PLL circuitry is the relatively long time for the output signal to "lock" onto the reference signal. Another disadvantage of PLL circuitry is a relatively narrow lock range. That is, a significant change in the reference signal cannot occur rapidly without the output signal falling out-of-lock. Typical approaches for maintaining lock include slowly incrementing/decrementing the reference signal so that the output signal can follow. This approach however, impacts performance by inducing latency. Yet another disadvantage of PLL circuitry is that analog circuitry is typically required for synthesizing higher frequencies.
By way of further background, DLL circuitry employs one or more delay lines coupled to the reference signal, one or more pulse generators, and one or more summing elements to reconstitute a clock signal having a desired period and frequency.
An advantage of DLL circuitry is quick lock-time. Another advantage of DLL circuitry is static or low frequency operation without induced latency. Yet another advantage with DLL circuitry is implementation with all digital elements.
A disadvantage however, with DLL circuitry is that temporal skew typically exists between the reference signal and the output signal.
Accordingly, it can be seen from the foregoing, that there is a need for clock generation circuitry and methodology that combines the meritorious attributes of both PLL and DLL circuitries.